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gl9714 pci express tm pipe x4 phy datasheet revision 1.32 apr. 16, 2007 genesys logic, inc.
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 2 copyright: copyright ? 2007 genesys logic incorporated. all rights reserv ed. no part of the materials may be reproduced in any form or by any means without prio r written consent of genesys logic, inc. disclaimer: all materials are provided ?as is? without express or implied warranty of any kind. no license or right is granted under any pat ent or trademark of genesys logic inc.. genesys logic hereby disclaims all warranties and conditions in regard to materials, including all wa rranties, implied or express, of merchantability, fitness for any particular purp ose, and non-infringement of intellectual property. in no event shall genesy s logic be liable for any damages including, without limitation, damages resu lting from loss of information or profits. please be advised that the materials may contain errors or ommisions. genesys logic may make change s to the materials or to the products described therein at any time without notice. trademarks: is a registered trademark of genesys logic, inc. all trademarks are the properties of their respect ive owners. office: genesys logic, inc. 12f, no. 205, sec. 3, beishin rd., shindian city, taipei, taiwan tel: (886-2) 8913-1888 fax: (886-2) 6629-6168 http ://www.genesyslogic.com
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 3 revision history revision date description 1.00 09/27/2004 first formal release 1.10 04/04/2005 update for mass production version 1.11 04/12/2005 revise register description(sw, dem), p.19 1.12 04/20/2005 1. add operating current for dc electrical characte ristics in table7.1 2. correct power consumption 1.13 09/20/2005 modify package dimension ,ch9 , p.39 1.14 10/13/2005 1. add ?bottom view?, ch3.1, p.10 2. change pin e15 from ?txdk1? to ?txdka?, table3.1 , p.11 3. change txdka~d type from ?o? to ?i?, table3.4, p .15 4. add a column ?i/o standard?, table3.4, p.15 5. change vddpll from ?c18? to ?c8?, table3.4, p.16 6. add comment for scc and opmode[1:0], table3.4 , p.17 1.16 11/15/2005 1. update table3.4, p.15~p.17 2. add table3.5, p.17 3. modify the default value of reg0 and reg1 in tab le4.1, p.18 4. modify ch4.2 registers descriptions for reg0 and reg1, p.19 5. add ch 4.3, p.21~p.24 6. update table 7.5 and table 7.6 for power consump tion, p.36~p.37 7. change txdx to rxdx, figure8.4, p.41 8. the minimum and maximum value of t cycle, table8.2 and table 8.5, p.42 1.17 12/15/2005 1. update table 7.9 for temperature ranges (p.39) 2. update table 8.1~8.4 for output delay of rx bus (p.41~p.42) 1.18 03/15/2006 1. modify the description of osc25mi and osc25mo si gnals, table 3.4, p.17 2. update table 7.1 for deleting i dd1-x4 , i dd2-x4 , i dd3-x4 , i dd1-x2 , i dd2-x2 , and i dd3-x2 six items, p.34 3. update table 7.9 for deleting the i supply-1.8 item and adding ja , jt and jc three items, p.39 1.19 03/28/2006 swap the pin out of osc25mi and osc25mo in table 3. 1~table 3.4. 1.20 03/30/2006 update table 7.9 for the illustration and the value of thermal parameters, p.39 1.21 04/26/2006 divide table 7.9 into table 7.9(temperature range) and table 7.10(thermal characteristics), p.39 1.22 05/08/2006 update fig. 8.1, 8.2 and table 8.1~8.5 for pipe inp ut and output timing characteristic, p.40~p.42 1.23 06/09/2006 update table 8.1~8.5 for the description of t co and t oh , p.41~p.42 1.24 06/20/2006 1.update table 3.5 for the parameter of buffer i/o, p.17 2.remove table 7.2, p.34 1.25 07/31/2006 1.remove ren and plpbk bits of smbus register regc, p.20 2.add reg14 ~ reg17 for slpbk error count result, p .21 3.add ?ps: please write ?0? to?? .? description, p.21 1.26 10/27/2006 add duty- h field for table 8.3 and table 8.5, p.43 1.30 02/06/2007 update table 8.1~8.5 for timing issue, p.42~44 1.31 03/19/2007 1. add a note to table 8.1, p.42 2. update table 7.4, 7.5 for the p ower consumption of reference voltage 1.25v, p37~p38, correct the index of table7.2, 7.3, p35 1.32 04/16/2007 complies with pci express base specification rev. 1 .1, p9
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 4 table of contents chapter 1 general description..................... .............................. 8 chapter 2 features ................................ .............................................. 9 chapter 3 pin assignment .......................... .................................... 10 3.1 p inout ................................................... .................................................. 1 0 3.2 b all o ut ................................................... .............................................. 10 3.3 p in l ist ................................................... ................................................. 11 3.4 p in d escriptions ................................................... ................................ 15 chapter 4 registers ............................... ........................................... 18 4.1 r egisters b ase a ddress ................................................... ................... 18 4.2 r egisters d escriptions ................................................... ................... 19 4.3 smb us p rotocol ................................................... ............................... 22 chapter 5 block diagram........................... ................................... 26 5.1 s implified d iagram ................................................... ........................... 26 5.2 t ransmitter d ata p ath p er l ane ................................................... . 27 5.3 r eceiver d ata p ath p er l ane ................................................... ........ 28 chapter 6 function description .................... ........................... 29 6.1 c lock and r eset ................................................... ................................ 29 6.2 r eceiver d etection ................................................... ......................... 29 6.3 b eacon t ransmitting and d etection .............................................. 29 6.4 r eceiver s tatus r eport ................................................... .................. 29 6.5 l oopback ................................................... ............................................. 30 6.6 p olarity i nversion ................................................... ........................... 30 6.7 s etting n egative d isparity ................................................... ............ 30 6.8 b ehavior s ummary ................................................... ........................... 31 6.9 p ower s aving s upport ................................................... ..................... 31 6.10 o peration m ode and m ulti -f unctional p ins ............................. 32 chapter 7 electrical characteristics.............. ................. 35 7.1 dc e lectrical c haracteristics ................................................... ... 35
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 5 7.2 t ransmit and r eceive l atency t ime .............................................. 35 7.3 t ransition t ime of p ower s tate ................................................... ... 35 7.4 p ower c onsumption ................................................... ......................... 37 7.5 d ifferential t ransmitter and r eceiver s erial o utput ........... 39 7.6 r ecommended o perating c onditions ............................................. 40 chapter 8 pipe timing characteristics ............. .................. 41 8.1 i nput s etup , h old t ime and o utput t iming ................................... 41 8.2 r eference t iming i nformation ................................................... ..... 44 chapter 9 package dimension....................... .............................. 45 chapter 10 ordering information ................... ....................... 46
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 6 list of figures f igure 3.1 - 233 p in lfbga p inout d iagram ................................................... ......... 10 f igure 4.1 ? smb us t opology of gl9714............................................. ..................... 22 f igure 4.2 ? d ata v alidity ................................................... ........................................ 22 f igure 4.3 ? start and stop c ondition ................................................... ............... 23 f igure 4.4 ? ack and nack s ignaling of smb us ................................................... 23 f igure 4.5 ? smb us p acket p rotocol d iagram e lement k ey ............................. 24 f igure 4.6 ? w rite b yte p rotocol ................................................... .......................... 24 f igure 4.7 ? r ead b yte p rotocol ................................................... ............................ 24 f igure 4.8 ? t he m inimum w ait t ime from p ower on to p rogramming r egisters ................................................... ................................................... ................... 25 f igure 5.1 - s implified d iagram ................................................... ............................... 26 f igure 5.2 - t ransmitter d ata p ath per l ane ................................................... ...... 27 f igure 5.3 - r eceiver d ata p ath per l ane ................................................... ............ 28 f igure 8.1 ? d efinition of i nput s etup and h old t ime .......................................... 41 f igure 8.2 ? d efinition of o utput t iming ................................................... .............. 42 f igure 9.1 - gl9714 233 p in lfbga p ackage ................................................... ........ 45
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 7 list of tables t able 3.1 - b all o ut ................................................... ................................................... . 10 t able 3.2 - n umeric p in l ist ................................................... ...................................... 11 t able 3.3 - a lphabetic p in l ist ................................................... ................................ 13 t able 3.4 - p in d escriptions ................................................... ...................................... 15 t able 3.5 - p arameter of b uffer i/o ................................................ ......................... 17 t able 4.1 - b ase a ddress for r egisters ................................................... ................. 18 t able 6.1 - p in f unctions ................................................... ........................................... 32 t able 7.1 - dc e lectrical c haracteristics ................................................... ......... 35 t able 7.2 - t ransmit and r eceive l atency t ime ................................................... . 35 t able 7.3 ? t ransition t ime of p ower s tate ................................................... ........ 35 t able 7.4 ? t ypical p ower c onsumption with 2-l anes , 4-l anes , and 1.2v d ifferential p eak to p eak o utput v oltage ................................................... ....... 37 t able 7.5 ? t ypical p ower c onsumption with s ingle -l ane and 1.2v d ifferential p eak to p eak o utput v oltage ................................................... ....... 38 t able 7.6 ? t ransmitter s erial o utput ................................................... ................. 39 t able 7.7 ? r eceiver s erial o utput ................................................... ....................... 40 t able 7.8 ? t emperature r ange ................................................... .............................. 40 t able 7.9 ? t hermal c haracteristics ................................................... ................... 40 t able 8.1 ? i nput s etup , h old t ime and o utput t iming for 8- bit sdr m ode ... 42 t able 8.2 ? i nput s etup , h old t ime and o utput t iming for 8- bit ddr m ode .. 43 t able 8.3 ? i nput s etup , h old t ime and o utput t iming for 16- bit m ode .......... 43 t able 8.4 ? i nput s etup , h old t ime and o utput t iming for 10- bit sdr m ode . 43 t able 8.5 ? i nput s etup , h old t ime and o utput t iming for 10- bit ddr m ode 44 t able 8.6 ? r eference t iming i nformation ................................................... .......... 44 t able 10.1 - o rdering i nformation ................................................... ........................ 46
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 8 chapter 1 general description the gl9714 is a 4-lane pci express phy layer contro ller, which is compliant with pci express base specification rev. 1.0a and intel?s phy interface f or the pci express architecture rev. 1.0. it integr ates a quad serdes and the physical coding sublayer (pcs) which performs 8b/10b encoding and decoding, elastic buf fer and receiver detection, data serialization and dese rialization for each lane. the quad serdes in the g l9714 supports an effective serial interface speed (2.5 g b/s) of data bandwidth for each lane, intended for use in ultrahigh-speed bi-directional data transmission sy stem. the gl9714 can also be externally configured for various combinations of lane number and parallel bu s width which is flexible and suitable for x1, x2 o r x4 lane implementation. it also supports four operational s tates for power management to minimize power consum ption. for production and self-test purposes, the gl9714 p rovides bist and an internal loopback capability. the primary application of this chip is to provide very high-speed i/o data channels for point-to-poin t baseband data transmission over an on-chip termination resis ter of 50 ohm +/- 10%. this device can also be used to replace parallel da ta transmission architectures by providing a reduct ion in the number of traces, connector pins, and transmit/rece ive pins. parallel data loaded into the transmitter is delivered to the receiver over a serial channel. it is then r econstructed into its original parallel format. the maximum data transfer rate in each direction is 1 giga byte per second with the 4-lane configuration. it also offer s various power saving modes to significantly reduce power co nsumption as well as scalability for a higher data rate in the future.
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 9 chapter 2 features complies with pci express base specification rev. 1 .1 complies with intel?s phy interface for pci express architecture rev. 1.0 integrates quad 2.5 gigabit per second (gbps) seria lizer/deserializer supports 8-bit or 10-bit parallel interface @250mhz for x1, x2 and x4 implementation supports 16-bit parallel interface @125mhz for x1 a nd x2 configuration supports ddr configuration for 8-bit or 10-bit mode beacon transmission and reception receiver detection transmission and detection of electrical idle clock tolerance for 600 ppm in frequencies between bit rates at the two end of a link on-chip 8-bit/10-bit encoding/decoding and comma al ignment on-chip pll provides clock synthesis 1.8-v power supply for core 2.5-v power supply for io above 2.0 kv esd protection 0.18 m process available in lfbga-233 package
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 10 chapter 3 pin assignment 3.1 pinout a bc d e f g h j k l n p r m t u 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bottom view figure 3.1 - 233 pin lfbga pinout diagram 3.2 ball out table 3.1 - ball out 1 2 3 4 5 6 7 8 9 a refclkp txnd vddtxd rxnd vddrxd txnc vddtxc rxnc vddrxc b refclkn txpd vsstxd rxpd vssrxd txpc vsstxc rxpc vssrxc c osc25mo rxdd7 nc vdd18 nc nc vsstxc vddpll nc d osc25mi vdd25 rxdd3 vss vss nc vdd18 rterm vsspll e rxdkd rxdd1 rxdd4 rxdd5 f vss rxstsd1 rxdd2 rxdd6 g txcmpd vdd25 rxstsd2 rxdd0 vss vss vss h txdd4 txdd6 txdd7 rxstsd0 vss vss vss j txdd2 vss txdd5 txdd3 vss vss vss k vdd25 txdd0 txdd1 vdd12 vss vss vss l vss vss txdkd vdd18 vss vss vss m vss rxdc7 vdd18 rxdc4 n rxdc5 vss rxdc6 rxdc0 p vdd25 rxdc1 rxdc2 rxstsc2 rxstsc0 txdc3 txdkc rxidled vss r rxdc3 rxstsc1 txcmpc txdc7 txdc5 txdc1 vss rxplrd opmode0
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 11 t rxdkc vdd25 txdc6 txdc2 vdd25 vdd18 txidled rxidlec rxplrc u vss txdc4 vss txdc0 physts rxvldd rxvldc txidlec vdd25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a txnb vddtxb rxnb vddrxb txna vddtxa rxna vddrxa b txpb vsstxb rxpb vssrxb txpa vsstxa rxpa vssrxa c vdd18 nc vdd18 nc txda1 vssgr txda6 txda7 d nc nc nc txda0 txda3 txda4 vdd25 rxstsa2 e txda5 txdka txda2 rxdka f rxstsa0 txcmpa rxda0 vdd25 g vss vss rxstsa1 rxda1 rxda2 rxda4 h vss vss rxda5 rxda3 rxda7 vdd18 j vss vss vdd12 vss rxda6 vdd18 k vss vss txdb2 vdd25 txdkb nc l vss vss txcmpb txdb6 txdb1 txdb0 m rxstsb1 txdb4 txdb3 vss n rxdb3 rxdkb txdb7 txdb5 p pd1 rxvldb rxvlda rxdb7 rxdb5 rxdb1 vss rxstsb0 r scc txdet/ lpbk txidleb vdd25 txidlea rxdb4 rxdb0 vdd25 t testd pd0 rxidleb rxidlea pclk vss rxdb2 rxstsb2 u opmode1 testc rst_n rxplrb vss rxplra rxdb6 vdd25 10 11 12 13 14 15 16 17 3.3 pin list table 3.2 - numeric pin list pin# pin name pin# pin name pin# pin name pin# pin name pin# pin name a1 refclkp c1 osc25mo e1 rxdkd g1 txcmpd j1 txdd2 a2 txnd c2 rxdd7 e2 rxdd1 g2 vdd25 j2 vss a3 vddtxd c3 nc e3 rxdd4 g3 rxstsd2 j3 txdd5 a4 rxnd c4 vdd18 e4 rxdd5 g4 rxdd0 j4 txdd3 a5 vddrxd c5 nc e5 g5 j5 a6 txnc c6 nc e6 g6 j6 a7 vddtxc c7 vsstxc e7 g7 vss j7 vss a8 rxnc c8 vddpll e8 g8 vss j8 vss a9 vddrxc c9 nc e9 g9 vss j9 vss a10 txnb c10 vdd18 e10 g10 vss j10 vss a11 vddtxb c11 nc e11 g11 vss j11 vss a12 rxnb c12 vdd18 e12 g12 j12 a13 vddrxb c13 nc e13 g13 j13
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 12 a14 txna c14 txda1 e14 txda5 g14 rxstsa1 j14 vdd12 a15 vddtxa c15 vssgr e15 txdka g15 rxda1 j15 vss a16 rxna c16 txda6 e16 txda2 g16 rxda2 j16 rxda6 a17 vddrxa c17 txda7 e17 rxdka g17 rxda4 j17 vdd18 b1 refclkn d1 osc25mi f1 vss h1 txdd4 k1 vdd25 b2 txpd d2 vdd25 f2 rxstsd1 h2 txdd6 k2 txdd0 b3 vsstxd d3 rxdd3 f3 rxdd2 h3 txdd7 k3 txdd1 b4 rxpd d4 vss f4 rxdd6 h4 rxstsd0 k4 vdd12 b5 vssrxd d5 vss f5 h5 k5 b6 txpc d6 nc f6 h6 k6 b7 vsstxc d7 vdd18 f7 h7 vss k7 vss b8 rxpc d8 rterm f8 h8 vss k8 vss b9 vssrxc d9 vsspll f9 h9 vss k9 vss b10 txpb d10 nc f10 h10 vss k10 vss b11 vsstxb d11 nc f11 h11 vss k11 vss b12 rxpb d12 nc f12 h12 k12 b13 vssrxb d13 txda0 f13 h13 k13 b14 txpa d14 txda3 f14 rxstsa0 h14 rxda5 k14 txdb2 b15 vsstxa d15 txda4 f15 txcmpa h15 rxda3 k15 vdd25 b16 rxpa d16 vdd25 f16 rxda0 h16 rxda7 k16 txdkb b17 vssrxa d17 rxstsa2 f17 vdd25 h17 vdd18 k17 nc pin# pin name pin# pin name pin# pin name pin # pin name l1 vss n1 rxdc5 r1 rxdc3 u1 vss l2 vss n2 vss r2 rxstsc1 u2 txdc4 l3 txdkd n3 rxdc6 r3 txcmpc u3 vss l4 vdd18 n4 rxdc0 r4 txdc7 u4 txdc0 l5 n5 r5 txdc5 u5 physts l6 n6 r6 txdc1 u6 rxvldd l7 vss n7 r7 vss u7 rxvldc l8 vss n8 r8 rxplrd u8 txidlec l9 vss n9 r9 opmode0 u9 vdd25 l10 vss n10 r10 scc u10 opmode1 l11 vss n11 r11 txdet/lpbk u11 testc l12 n12 r12 txidleb u12 rst_n l13 n13 r13 vdd25 u13 rxplrb l14 txcmpb n14 rxdb3 r14 txidlea u14 vss l15 txdb6 n15 rxdkb r15 rxdb4 u15 rxplra
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 13 l16 txdb1 n16 txdb7 r16 rxdb0 u16 rxdb6 l17 txdb0 n17 txdb5 r17 vdd25 u17 vdd25 m1 vss p1 vdd25 t1 rxdkc m2 rxdc7 p2 rxdc1 t2 vdd25 m3 vdd18 p3 rxdc2 t3 txdc6 m4 rxdc4 p4 rxstsc2 t4 txdc2 m5 p5 rxstsc0 t5 vdd25 m6 p6 txdc3 t6 vdd18 m7 p7 txdkc t7 txidled m8 p8 rxidled t8 rxidlec m9 p9 vss t9 rxplrc m10 p10 pd1 t10 testd m11 p11 rxvldb t11 pd0 m12 p12 rxvlda t12 rxidleb m13 p13 rxdb7 t13 rxidlea m14 rxstsb1 p14 rxdb5 t14 pclk m15 txdb4 p15 rxdb1 t15 vss m16 txdb3 p16 vss t16 rxdb2 m17 vss p17 rxstsb0 t17 rxstsb2 blank table 3.3 - alphabetic pin list pin name pin# pin name pin# pin name pin# pin name pin# pin name pin# nc c3 rxdd0 g4 txcmpa f15 txnc a6 vss h7 nc c5 rxdd1 e2 txcmpb l14 txnd a2 vss h8 nc c6 rxdd2 f3 txcmpc r3 txpa b14 vss h9 nc c9 rxdd3 d3 txcmpd g1 txpb b10 vss h10 nc c11 rxdd4 e3 txda0 d13 txpc b6 vss h11 nc c13 rxdd5 e4 txda1 c14 txpd b2 vss j2 nc d6 rxdd6 f4 txda2 e16 vdd12 j14 vss j7 nc d10 rxdd7 c2 txda3 d14 vdd12 k4 vss j8 nc d11 rxdka e17 txda4 d15 vdd18 c4 vss j9 nc d12 rxdkb n15 txda5 e14 vdd18 c10 vss j10 nc k17 rxdkc t1 txda6 c16 vdd18 c12 vss j11 opmode0 r9 rxdkd e1 txda7 c17 vdd18 d7 vss j15 opmode1 u10 rxidlea t13 txdb0 l17 vdd18 h17 vss k7 osc25mo c1 rxidleb t12 txdb1 l16 vdd18 j17 vss k8 osc25mi d1 rxidlec t8 txdb2 k14 vdd18 l4 vss k9 pclk t14 rxidled p8 txdb3 m16 vdd18 m3 vss k10
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 14 pd0 t11 rxna a16 txdb4 m15 vdd18 t6 vss k11 pd1 p10 rxnb a12 txdb5 n17 vdd25 d2 vss l1 physts u5 rxnc a8 txdb6 l15 vdd25 d16 vss l2 refclkn b1 rxnd a4 txdb7 n16 vdd25 f17 vss l7 refclkp a1 rxpa b16 txdc0 u4 vdd25 g2 vss l8 rst_n u12 rxpb b12 txdc1 r6 vdd25 k1 vss l9 rterm d8 rxpc b8 txdc2 t4 vdd25 k15 vss l10 rxda0 f16 rxpd b4 txdc3 p6 vdd25 p1 vss l11 rxda1 g15 rxplra u15 txdc4 u2 vdd25 r13 vss m1 rxda2 g16 rxplrb u13 txdc5 r5 vdd25 r17 vss m17 rxda3 h15 rxplrc t9 txdc6 t3 vdd25 t2 vss n2 rxda4 g17 rxplrd r8 txdc7 r4 vdd25 t5 vss p9 rxda5 h14 rxstsa0 f14 txdd0 k2 vdd25 u9 vss p16 rxda6 j16 rxstsa1 g14 txdd1 k3 vdd25 u17 vss r7 rxda7 h16 rxstsa2 d17 txdd2 j1 vddpll c8 vss t15 rxdb0 r16 rxstsb0 p17 txdd3 j4 vddrxa a17 vss u1 rxdb1 p15 rxstsb1 m14 txdd4 h1 vddrxb a13 vss u3 rxdb2 t16 rxstsb2 t17 txdd5 j3 vddrxc a9 vss u14 rxdb3 n14 rxstsc0 p5 txdd6 h2 vddrxd a5 vssgr c15 rxdb4 r15 rxstsc1 r2 txdd7 h3 vddtxa a15 vsspll d9 rxdb5 p14 rxstsc2 p4 txdet/lpbk r11 vddtxb a11 vssrxa b17 rxdb6 u16 rxstsd0 h4 txdka e15 vddtxc a7 vssrxb b13 rxdb7 p13 rxstsd1 f2 txdkb k16 vddtxd a3 vssrxc b9 rxdc0 n4 rxstsd2 g3 txdkc p7 vss d4 vssrxd b5 rxdc1 p2 rxvlda p12 txdkd l3 vss d5 vsstxa b15 rxdc2 p3 rxvldb p11 txidlea r14 vss f1 vsstxb b11 rxdc3 r1 rxvldc u7 txidleb r12 vss g7 vsstxc b7 rxdc4 m4 rxvldd u6 txidlec u8 vss g8 vsstxc c7 rxdc5 n1 scc r10 txidled t7 vss g9 vsstxd b3 rxdc6 n3 testc u11 txna a14 vss g10 rxdc7 m2 testd t10 txnb a10 vss g11
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 15 3.4 pin descriptions table 3.4 - pin descriptions pipe interface pin name i/o standard pin# type description rst_n lvcmos2 u12 i global reset pclk sstl2_i t14 o parallel interface clock all data movement across the parallel interface is synchronous to this clock. 1. for 8-bit mode: pclk operates at 250 mhz and is applied to synchronize all txdx, rxdx data bus and all commands. 2. for 16-bit mode: pclk operates at 125 mhz and is applied to synchronize all txdx, rxdx data bus and all commands. 3. for 10-bit mode(tbc): pclk operates at 250 mhz and is applied to synchronize the txdx data bus and all commands. rxstsa[2:0] rxstsb[2:0] rxstsc[2:0] rxstsd[2:0] sstl2_i d17, g14, f14 t17, m14, p17 p4, r2, p5 g3, f2, h4 o 1. for 8-bit and 16-bit modes: encodes receiver status and error codes for the received data stream and receiver detection 000 received data ok 001 1 skp added 010 1 skp removed 011 receiver detected 100 8b/10b decode error 101 elastic buffer overflow 110 elastic buffer underflow 111 receiver disparity error 2. for 10-bit modes: rxstsx[2]: rbcx, synchronize the rxdx data bus rxstsx[1]: rxprsntx, report the result of receiver detection rxstsx[0]: rxdx9, bit 9 of rxdx data bus rxidlea~d lvcmos2 t13, t12, t8, p8 o indicates receiver detection of an electrical idle this is an asynchronous signal. physts sstl2_i u5 o used to communicate completion of several phy functions including power state transitions and receiver detection rxvlda~d lvcmos2 p12, p11, u7, u6 o indicates symbol lock and valid data on rxdx and rxdkx txcmpa~d sstl2_i f15, l14, r3, g1 i sets the running disparity to negative txidlea~d lvcmos2 r14, r12, u8, t7 i forces tx output to electrical idle rxdka~d sstl2_i e17, n15, t1, e1 o k-code indication for the received symbols rxda[7:0] sstl2_i h16, j16, h14, g17, h15, g16, g15, f16 o parallel data output bus
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 16 rxdb[7:0] rxdc[7:0] rxdd[7:0] p13, u16, p14, r15, n14, t16, p15, r16 m2, n3, n1, m4, r1, p3, p2, n4 c2, f4, e4, e3, d3, f3, e2, g4 txdka~d sstl2_i e15, k16, p7, l3 i k-code indication for the transmitted symbols txda[7:0] txdb[7:0] txdc[7:0] txdd[7:0] sstl2_i c17, c16, e14, d15, d14, e16, c14, d13 n16, l15, n17, m15, m16, k14, l16, l17 r4, t3, r5, u2, p6, t4, r6, u4 h3, h2, j3, h1, j4, j1, k3, k2 i parallel data input bus txdet/lpbk lvcmos2 r11 i receiver detection/loopback pd[1:0] lvcmos2 p10, t11 i sets the power states 00 p0, normal operation 01 p0s, low recovery time latency, power saving state 10 p1, longer recovery time(64us max) latency, lower power state 11 p2, lowest power state rxplra~d lvcmos2 u15, u13, t9, r8 i inverts the polarity on the rxp/rxn power and ground signals pin name pin# type description vdd25 d2, d16, f17, g2, k1, k15, p1, r13, r17, t2, t5, u9, u17 p 2.5v power supplies for general i/o vdd18 c4, c10, c12, d7, h17, j17, l4, m3, t6 p 1.8v power supplies for core and bias voltage vdd12 j14, k4 p 1.25v reference voltage for high sp eed i/o vss d4, d5, f1, g7, g8, g9, g10, g11, h7, h8, h9, h10, h11, j2, j7, j8, j9, j10, j11, j15, k7, k8, k9, k10, k11, l1, l2, l7, l8, l9, l10, l11, m1, m17, n2, p9, p16, r7, t15, u1, u3, u14 p digital ground vddpll c8 p 1.8v power supplies for internal pll vsspll d9 p ground for internal pll vddrxa~d vssrxa~d a17, a13, a9, a5 b17, b13 , b9, b5 p 1.8v power supplies for receiver part vddtxa~d vsstxa~d a15, a11, a7, a3 b15, b11, b7, c7, b3 p 1.8v power supplies for transceiver part vssgr c15 p ground for the guard ring of the serdes block serial signals pin name pin# type description rxna~d a16, a12, a8, a4 i received serial input, co mplement rxpa~d b16, b12, b8, b4 i received serial input, true rterm d8 i connects an external 5.1k resistor to ground
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 17 for calibrating the on-chip termination resistors txna~d a14, a10, a6, a2 o transmitted serial output , complement txpa~d b14, b10, b6, b2 o transmitted serial output, true other signals pin name i/o standard pin# type description refclkp analogue a1 i reference clock signal refclkn analogue b1 i reference clock signal osc25mo crystal c1 o connect to 25mhz crystal when using crystal as the reference clock source osc25mi crystal/ oscillator d1 i connect to 25mhz crystal/oscillator when using crystal/oscillator as the reference clock source testc/smc lvcmos2 u11 i test clock/smbus clock testd/smd lvcmos2 t10 i/o test data/smbus data scc lvcmos2 r10 i configures clock input source when scc=1, the chip clock sources from a pair of differential signals, refclkp and refclkn, with a nominal frequency of 100 mhz. when scc=0, the chip clock sources from a crystal at 25mhz. opmode[1:0] lvcmos2 u10, r9 i operational mode of the gl9714 00 4 lanes, 8 bit mode 01 2 lanes, 16 bit mode 10 4 lanes, 10 bit mode 11 internal use only nc - c3, c5, c6, c9, c11, c13, d6, d10, d11, d12, k17 - no connection table 3.5 - parameter of buffer i/o v ih (input high voltage, v) v il (input low voltage , v) v oh (output high voltage, v) v ol (output low voltage, v) buffer type min norm max min norm max min norm max min norm max lvcmos2 1.7 - - - - 0.7 2.4 - - - - 0.4 sstl2 1.57 - - - - 0.93 1.76 - - - - 0.74
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 18 chapter 4 registers there are some registers built-in the gl9714 for te st purpose. these registers can be accessed through a serial bus interface using pin testc and testd. registers at offset 05h ~ 0bh are for internal test only. ple ase be careful to leave them as default values. 4.1 registers base address table 4.1 - base address for registers mnemonic offset description default revid 00h revision id and auto-calibration result r egister 8?bxxxx0xxx xcvropt 01h transceiver option register 8?he9 lpbktest 02h bist and beacon/test data pattern register, par t 1 8?h00 bcnpat2 03h beacon/test data pattern register, part 2 8?h03 bcnpat3 04h beacon/test data pattern register, part 3 8?hff - 05h for internal test only - - 06h for internal test only - - 07h for internal test only - - 08h for internal test only - - 09h for internal test only - - 0ah for internal test only - - 0bh for internal test only - bt 0ch buffer test register 8?h00 slcdt 0dh serial loopback and comma detect test reg ister 8?h00 notation: r/w read / write r/o read only w/o write only r/w1c read / write ?1? to clear r/w/c read / write and hardware automatic clear
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 19 4.2 registers descriptions offset 00h ? revid ?????????????? ?? ?.???? default value = 8?bxxxx0xxx rev3 rev2 rev1 rev0 by1 rcal0 rcal1 rcal2 r r r r r r r r 7-4 rev[3:0] chip revision code 3 by1 x1 package 2-0 rcal[0:2] calibration result of on-chip termination resistors offset 01h ? xcvropt ????????????????? ..???? . default value = 8?he9 sw1 sw0 dem1 dem0 bw0 bw1 rdef feval r/w r/w r/w r/w r/w r/w r/w r/w 7-6 sw[1:0] swing control of transmitter output output swing (differential, peak-to-peak) 00 0.6v 01 0.8v 10 1.0v 11 1.2v 5-4 dem[1:0] de-emphasis control of transmitter output amount of de-emphasis 00 no de-emphasis 01 -1.6db 10 -3.5db 11 -6.0db 3-2 bw[0:1] bandwidth control of clock recovery circuit relative bandwidth 00 1 01 2 10 4 11 reserved 1 rdef disable calibration of on-chip termination resistor s and leave the resistors to their default value 0 feval force calibration of on-chip termination resistors when rdef =0, writing a one to this bit will make the resistors re-calibrated. thi s bit is auto-cleared and always read as zero.
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 20 offset 02h ? lpbktest ???????????????? ..???? . default value = 8?h00 bist0 bist1 bist2 -- bcn19 bcn18 bcn17 bcn16 r/w r/w r/w -- r/w r/w r/w r/w 7-5 bist[0:2] select of built-in test pattern bit pattern 00x bist disabled 100 0000000000 0000000000 010 1111111111 1111111111 110 0101010101 0101010101 101 0011111010 1010101010 1100000101 0101010101 011 0011111010 1010 0 * 01010 1100000101 0101 1 * 10101 111 prbs pattern it should be noted that the expected pattern while bist[0:2]=011 is the same as bist[0:2]=101. but when coming out of the transmitt er, the two bits with ? * ? in bist[0:2]=011 are different from bist[0:2]=101. as a result, even when there is no bit error, there will be bit errors intentionall y introduced to verify the bist circuit is functional. 4 reserved - 3-0 bcn[19:16] data pattern for beacon and txtest offset 03h ? bcnpat2 ???????????????? ?? ?.?? . default value = 8?h03 bcn15 bcn14 bcn13 bcn12 bcn11 bcn10 bcn9 bcn8 r/w r/w r/w r/w r/w r/w r/w r/w 7-0 bcn[15:8] data pattern for beacon and txtest offset 04h ? bcnpat3 ?? ?????????????? ??? .?? . default value = 8?hff bcn7 bcn6 bcn5 bcn4 bcn3 bcn2 bcn1 bcn0 r/w r/w r/w r/w r/w r/w r/w r/w 7-0 bcn[7:0] data pattern for beacon and txtest offset 0ch ? bt ?? ??? ...??????????? ????? ...?? . default value = 8?h00 -- -- ddr -- txtest -- skpdel skpadd -- -- r/w -- r/w -- r/w r/w 7-6 reserved - 5 ddr enable ddr at pipe interface and make pclk = 125mhz @ 8/10-bit mode 3 txtest enable transmitter test with data pattern bcn[19:0] , which are programmed in reg02h, 03h and 04h 1 skpdel enable skp deleting test of skp ordered sets 0 skpadd enable skp adding test of skp ordered sets
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 21 offset 0dh ? slcdt ??? ...??????????? ????? ...?? . default value = 8?h00 slpbka slpbkb slpbkc slpbkd fencda fencdb fencdc fencdd r/w r/w r/w r/w r/w r/w r/w r/w 7 slpbka enable serial loopback of lane a 6 slpbkb enable serial loopback of lane b 5 slpbkc enable serial loopback of lane c 4 slpbkd enable serial loopback of lane d 3 fencda force comma detect of lane a 2 fencdb force comma detect of lane b 1 fencdc force comma detect of lane c 0 fencdd force comma detect of lane d offset 14h ? secnta ??? ...??????????? ????? ...?? . default value = 8?h00 secnta7 secnta6 secnta5 secnta4 secnta3 secnta2 secnta1 secnta0 r r r r r r r r 7-0 secnta[7:0] error count of slpbka. offset 15h ? secntb ??? ...??????????? ????? ...?? . default value = 8?h00 secntb7 secntb6 secntb5 secntb4 secntb3 secntb2 secntb1 secntb0 r r r r r r r r 7-0 secntb[7:0] error count of slpbkb. offset 16h ? secntc ??? ...??????????? ????? ...?? . default value = 8?h00 secntc7 secntc6 secntc5 secntc4 secntc3 secntc2 secntc1 secntc0 r r r r r r r r 7-0 secntc[7:0] error count of slpbkc. offset 17h ? secntd ??? ...??????????? ????? ...?? . default value = 8?h00 secntd7 secntd6 secntd5 secntd4 secntd3 secntd2 secntd1 secntd0 r r r r r r r r 7-0 secntd[7:0] error count of slpbkd. ps: please write ?0? to the unused bits when progra mming a register.
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 22 4.3 smbus protocol gl9714 registers are programmed by system managemen t bus (smbus). fig. 4.1 shows the smbus topology. the v dd power is 2.5v +/- 10% and the pull up resistor is 1 k . both smbclk and smbdat lines are bi-directional, connected to 2.5v supply voltage through a pull-up resistor. the operating f requency is 10~100khz and the smbus address of gl9714 is 7?h 2c. figure 4.1 ? smbus topology of gl9714 smbus uses fixed voltage levels to define the logic ?zero? and logic ?one? on the bus respectively. th e data on smbdat must be stable during the ?high? period o f the clock. data can change state only when smbclk is low. fig. 4.2 illustrates the relationships. figure 4.2 ? data validity
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 23 two unique bus situations define a message start an d stop condition. 1. a high to low transition of the smbdat line whil e smbclk is high indicates a message start condition. 2. a low to high transition of the smbdat line whil e smbclk is high defines a message stop condition. figure 4.3 ? start and stop condition every byte consists of 8 bits. each byte transferre d on the bus must be followed by an acknowledge bit . bytes are transferred with the most significant bit (msb) first. fig. 4.4 illustrates the positioning of ack nowledge (ack) and not acknowledge (nack) pulses relative to other data. figure 4.4 ? ack and nack signaling of smbus
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 24 below is a key to the protocol diagrams. s start condition sr repeated start condition rd read (bit value of 1) wr write (bit value of 0) x shown under a field indicates that that ` field is required to have the value of ?x ? a acknowledge (this bit position may be ?0? for an ack or ?1? for a nack) p stop condition master-to-gl9714 gl9714-to-master figure 4.5 ? smbus packet protocol diagram element key the first byte of a write byte access is the comman d code. the next one byte is the data to be written . in this example the master asserts gl9714?s address followe d by the write bit. gl9714 acknowledges and the mas ter delivers the command code. gl9714 again acknowledge s before the master sends the data byte. gl9714 acknowledges the data byte, and the entire transact ion is finished with a stop condition. figure 4.6 ? write byte protocol reading data is slightly more complicated than writ ing data. first the host must write a command to gl 9714. then it must follow that command with a repeated st art condition to denote a read from gl9714?s addres s. gl9714 then returns one byte of data. note that there is no stop condition before the rep eated start condition, and that a nack signified th e end of the read transfer. figure 4.7 ? read byte protocol
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 25 gl9714 requires a minimum time (16us) to reach the steady state after power on. so the master must sta rt programming at least 16us later after power on. figure 4.8 ? the minimum wait time from power on to programming registers
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 26 chapter 5 block diagram 5.1 simplified diagram pcs operational registers test bus controller quad serdes pll phy/mac interface configuration txpa txpc txna txnc rxpa rxpc rxna rxnc txpb txpd txnb txnd rxpb rxpd rxnb rxnd refclkp refclkn figure 5.1 - simplified diagram
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 27 5.2 transmitter data path per lane data x16 or x8 optional 16, 8-bit x8 8b 10b encoding x10 parallel to serial conversion transmitter differential driver txp txn txidle txdet/lpbk pclk 250 mhz txcmp txdk0,txdk1 2.5 ghz from pll loopback path from receiver figure 5.2 - transmitter data path per lane
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 28 5.3 receiver data path per lane differential recieiver data recovery circuit (drc) serial to paralle elastic buffer loopback path to transmitter rxn rxp rxidle clock recovery circuit 2.5 ghz k28.5 detection rxvld rxplr receiver status rxsts x10 x10 8b 10b decoder x8 optional 8, 16-bit data x16 or x8 rxdk recovered symbol clock buffer overflow/underflow skp added/removed decode error disparity error 250 mhz pcl figure 5.3 - receiver data path per lane
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 29 chapter 6 function description 6.1 clock and reset the clock source of the gl9714 comes externally from either the 100 mhz differential clock pair or the 2 5mhz crystal, which is selectable by pin scc. the gl9714 uses the clock source with its pll to generate the 2.5 ghz bit rate for transmitting and receiving. the gl9714 also drives a clock output for the synch ronization of mac interface. since the mac interfac e can be configured to 8-bit and 16-bit mode, the clock, pclk, runs at 250 mhz for 8-bit mode and 125 mhz fo r 16-bit mode. the mac should use the rising edge of the clock to send and receive parallel data. to initialize the gl9714, the mac should assert the reset of the gl9714 to low. while the reset is ass erted, the mac should also make txdet/lpbk deasserted, txidlex asserted, txcmpx deasserted, rxplrx deasserted and pd[1:0] = p1. when the gl9714 senses it reset asserted, it will drive its physts high immediately. after the reset deasserted, the gl9714 requires typically 16.7us for internal pll stable and then transitions its physts to low. when mac deasserts t he reset, it should monitor the state of physts to make sure the gl9714 is ready for normal operation. 6.2 receiver detection the receiver detection can only be performed while the gl9714 is in p1 state. to instruct the gl9714 t o enter a receiver detection sequence, the mac asserts txdet/ lpbk and hold it asserted until the gl9714 asserts physts for response. while finishing the receiver d etection, the gl9714 will assert physts and present a appropriate value to rxstsx[2:0] to signal a detect ion completion. when the mac detects physts asserte d, it knows the detection result from rxstsx[2:0] and can deassert txdet/lpbk. 6.3 beacon transmitting and detection beacon transmitting is required for the gl9714 in p 2 state to wake up the receiver in the other side o f the link. when the gl9714 is in p2 state, the mac can deasser t txidlex to instruct the gl9714 to repeatedly tran smit a beacon. for the beacon receiving side, if the gl9714 receiv es a beacon, it will transition rxidlex to low to i ndicate an exit from electrical idle. when the gl9714 is in p2 state and mac senses the rxidlex transitioned from high to low, it knows a beacon has been detected. 6.4 receiver status report add and remove a skp the gl9714 implements an elastic buffer to compensa te the clock rate difference between the recovery cl ock and its transmit clock. while receiving a skp order ed-set, compliant to pci express base specification rev. 1.0a, the gl9714 can insert or remove one skp symbol in the skp ordered-set to avoid the buffer overrun or underrun. whenever adding or removing a skp symbol, the gl9714 will signal physts and corresponding rxsts[2:0] to mac. skp ordered-set received rxsts code add a skp 001b remove a skp 010b receiver detected detected result rxsts code receiver not present 000b receiver present 011b
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 30 8b/10b decode error when the gl9714 decodes the received 10-bit symbol and detects an error code which does not correspond to any valid data, it will replace the c ode with an edb symbol, assert physts and encode rxstsx[2:0] with the values of decode error status, 3?b100. elastic buffer overrun and underrun when the overrun or underrun of the elastic buffer occurs, the gl9714 will assert physts and encode rxstsx[2:0] with the values of decode error status. elastic buffer rxsts code overrun 101b underrun 110b in the case of elastic buffer overrun, the gl9714 d rops the symbol. for the elastic buffer underrun, t he gl9714 inserts the edb symbol. the physts and rxsts x[2:0] are presented on the mac interface during the clock cycle where gl9714 drops or insert s the symbol. disparity errors to report a disparity error detected, the gl9714 as serts physts and encodes rxstsx[2:0] with the values of decode error status, 3?b111. 6.5 loopback the gl9714 supports a loopback mode to re-transmit its received data. when the mac sets the gl9714 in p0 state and asserts txdet/lpbk, the gl9714 enters a l oopback. in loopback, the gl9714 transmits data fro m it received data instead of mac interface. meanwhil e, it presents the received data on the mac interfa ce as normal operation. when set into loopback mode and acting as a loopbac k slave according to the pci express base specifica tion rev. 1.0a, the gl9714 received data from the loopba ck master. if the master intends to end the loopbac k, it sends an electrical idle ordered-set to the gl9714. when the mac detects the electrical idle ordered-s et, it de-asserts txdet/lpbk and asserts txidle to instruc t the gl9714 to stop loopback. the mac should take care the gl9714 has retransmit at least three bytes of the electrical idle before it makes the gl9714? s transmitter into electrical idle. 6.6 polarity inversion the gl9714 supports lane polarity inversion. while pin rxplrx asserted, the gl9714 inverts its receive d data on the mac interface. 6.7 setting negative disparity to set the running disparity to negative, the mac a sserts txcmpx for one pclk cycle that matches with the data that is to be transmitted where running dispar ity is negative.
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 31 6.8 behavior summary pd[1:0] txdet/lpbk txidlex behavior 0 0 gl9714 is transmitting data from mac interface norma lly. 0 1 gl9714 is not transmitting and is in electrical idle. 1 0 gl9714 enters loopback mode. p0 1 1 illegal x 0 illegal p0s x 1 gl9714 is not transmitting and is in electrical idle. x 0 illegal 0 1 gl9714 is idle. p1 1 1 gl9714 performs a receiver detection. x 0 gl9714 transmits a beacon. p2 x 1 gl9714 is idle. 6.9 power saving support the gl9714 supports four power states including p0, p0s, p1 and p2 and can be controlled to perform ac tive state power management on a pci express link. p0 is the normal operational state where data and contro l packets can be transmitted and received. when direc ted from p0 to a lower power state, the gl9714 can immediately take appropriate power saving actions. the power saving scheme of the gl9714 for various p ower down states is listed in the table below. pd[1:0] transmitter receiver pll pclk output p0 on on on on p0s high-impedance electrical idle on on on p1 high-impedance electrical idle off but exit from electrical idle is detectable on on p2 high-impedance electrical idle (capable of transmitting a beacon) off but exit from electrical idle is detectable off off
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 32 6.10 operation mode and multi-functional pins there are four modes for gl9714 operation which is selected by pin opmode[1:0]. mode [1] [0] description 1 0 0 4 lanes, 8 bit mode 2 0 1 2 lanes, 16 bit mode 3 1 0 4 lanes, 10 bit mode 4 1 1 for scan test only mode 1 : the gl9714 is configured into an x4 lane, 8-bit para llel bus and acts as a 4-lane pci express phy. the parallel bus is synchronous with pclk at 250 m hz. by transitioning both txcmpx and txidlex to high for individual lane, the gl9714 in t his mode is able to behave as an x1 or x2 phy. mode 2 : the gl9714 acts as a 2-lane phy with a 16-bit par allel interface at 125 mhz. in this mode, only lane b and lane c are activated. again, by disabli ng either lane using txcmpx and txidlex, the gl9714 can be configured into an x1 phy with16 -bit parallel bus. mode 3 : the gl9714 is configured as a quad serdes with 10 -bit parallel bus. mode 4 : for scan test only table 6.1 - pin functions pin number mode 1 mode 2 mode 3 t14 pclk(o) pclk(o) tbc(o) c17 txda7(i) txdb15(i) tda7(i) c16 txda6(i) txdb14(i) tda6(i) e14 txda5(i) txdb13(i) tda5(i) d15 txda4(i) txdb12(i) tda4(i) d14 txda3(i) txdb11(i) tda3(i) e16 txda2(i) txdb10(i) tda2(i) c14 txda1(i) txdb9(i) tda1(i) d13 txda0(i) txdb8(i) tda0(i) n16 txdb7(i) txdb7(i) tdb7(i) l15 txdb6(i) txdb6(i) tdb6(i) n17 txdb5(i) txdb5(i) tdb5(i) m15 txdb4(i) txdb4(i) tdb4(i) m16 txdb3(i) txdb3(i) tdb3(i) k14 txdb2(i) txdb2(i) tdb2(i) l16 txdb1(i) txdb1(i) tdb1(i) l17 txdb0(i) txdb0(i) tdb0(i) r4 txdc7(i) txdc15(i) tdc7(i) t3 txdc6(i) txdc14(i) tdc6(i) r5 txdc5(i) txdc13(i) tdc5(i) u2 txdc4(i) txdc12(i) tdc4(i) p6 txdc3(i) txdc11(i) tdc3(i) t4 txdc2(i) txdc10(i) tdc2(i) r6 txdc1(i) txdc9(i) tdc1(i) u4 txdc0(i) txdc8(i) tdc0(i) h3 txdd7(i) txdc7(i) tdd7(i)
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 33 h2 txdd6(i) txdc6(i) tdd6(i) j3 txdd5(i) txdc5(i) tdd5(i) h1 txdd4(i) txdc4(i) tdd4(i) j4 txdd3(i) txdc3(i) tdd3(i) j1 txdd2(i) txdc2(i) tdd2(i) k3 txdd1(i) txdc1(i) tdd1(i) k2 txdd0(i) txdc0(i) tdd0(i) e15 txdka(i) txdkb1(i) tda8(i) k16 txdkb(i) txdkb0(i) tdb8(i) p7 txdkc(i) txdkc1(i) tdc8(i) l3 txdkd(i) txdkc0(i) tdd8(i) r14 txidlea(i) txidlea(i) r12 txidleb(i) txidleb(i) txidleb(i) u8 txidlec(i) txidlec(i) txidlec(i) t7 txidled(i) txidled(i) f15 txcmpa(i) tda9(i) l14 txcmpb(i) txcmpb(i) tdb9(i) r3 txcmpc(i) txcmpc(i) tdc9(i) g1 txcmpd(i) tdd9(i) u15 rxplra(i) rxplra(i) u13 rxplrb(i) rxplrb(i) rxplrb(i) t9 rxplrc(i) rxplrc(i) rxplrc(i) r8 rxplrd(i) rxplrd(i) h16 rxda7(o) rxdb15(o) rda7(o) j16 rxda6(o) rxdb14(o) rda6(o) h14 rxda5(o) rxdb13(o) rda5(o) g17 rxda4(o) rxdb12(o) rda4(o) h15 rxda3(o) rxdb11(o) rda3(o) g16 rxda2(o) rxdb10(o) rda2(o) g15 rxda1(o) rxdb9(o) rda1(o) f16 rxda0(o) rxdb8(o) rda0(o) p13 rxdb7(o) rxdb7(o) rdb7(o) u16 rxdb6(o) rxdb6(o) rdb6(o) p14 rxdb5(o) rxdb5(o) rdb5(o) r15 rxdb4(o) rxdb4(o) rdb4(o) n14 rxdb3(o) rxdb3(o) rdb3(o) t16 rxdb2(o) rxdb2(o) rdb2(o) p15 rxdb1(o) rxdb1(o) rdb1(o) r16 rxdb0(o) rxdb0(o) rdb0(o) m2 rxdc7(o) rxdc15(o) rdc7(o) n3 rxdc6(o) rxdc14(o) rdc6(o) n1 rxdc5(o) rxdc13(o) rdc5(o) m4 rxdc4(o) rxdc12(o) rdc4(o) r1 rxdc3(o) rxdc11(o) rdc3(o) p3 rxdc2(o) rxdc10(o) rdc2(o)
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 34 p2 rxdc1(o) rxdc9(o) rdc1(o) n4 rxdc0(o) rxdc8(o) rdc0(o) c2 rxdd7(o) rxdc7(o) rdd7(o) f4 rxdd6(o) rxdc6(o) rdd6(o) e4 rxdd5(o) rxdc5(o) rdd5(o) e3 rxdd4(o) rxdc4(o) rdd4(o) d3 rxdd3(o) rxdc3(o) rdd3(o) f3 rxdd2(o) rxdc2(o) rdd2(o) e2 rxdd1(o) rxdc1(o) rdd1(o) g4 rxdd0(o) rxdc0(o) rdd0(o) e17 rxdka(o) rxdkb1(o) rda8(o) n15 rxdkb(o) rxdkb0(o) rdb8(o) t1 rxdkc(o) rxdkc1(o) rdc8(o) e1 rxdkd(o) rxdkc0(o) rdd8(o) p12 rxvlda(o) rxvlda(o) p11 rxvldb(o) rxvldb(o) rxvldb(o) u7 rxvldc(o) rxvldc(o) rxvldc(o) u6 rxvldd(o) rxvldd(o) d17 rxstsa2(o) rbca(o) g14 rxstsa1(o) rxprsnta(o) f14 rxstsa0(o) rda9(o) t17 rxstsb2(o) rxstsb2(o) rbcb(o) m14 rxstsb1(o) rxstsb1(o) rxprsntb(o) p17 rxstsb0(o) rxstsb0(o) rdb9(o) p4 rxstsc2(o) rxstsc2(o) rbcc(o) r2 rxstsc1(o) rxstsc1(o) rxprsntc(o) p5 rxstsc0(o) rxstsc0(o) rdc9(o) g3 rxstsd2(o) rbcd(o) f2 rxstsd1(o) rxprsntd(o) h4 rxstsd0(o) rdd9(o) u5 physts(o) physts(o) physts(o) t13 rxidlea(o) rxidlea(o) t12 rxidleb(o) rxidleb(o) rxidleb(o) t8 rxidlec(o) rxidlec(o) rxidlec(o) p8 rxidled(o) rxidled(o)
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 35 chapter 7 electrical characteristics 7.1 dc electrical characteristics table 7.1 - dc electrical characteristics symbol parameter min typ max unit vdd25 phy interface voltage 2.375 2.5 2.625 v vdd18 core voltage 1.71 1.8 1.89 v vdd12 reference voltage for phy interface 1.1875 1.25 1.3125 v vddtxa vddtxb vddtxc vddtxd voltage for transmitters 1.71 1.8 1.89 v vddrxa vddrxb vddrxc vddrxd voltage for receivers 1.71 1.8 1.89 v vddpll voltage for pll 1.71 1.8 1.89 v 7.2 transmit and receive latency time table 7.2 - transmit and receive latency time symbol parameter min typ max unit t tx-lat transmit latency, time for data moving from mac interface (pclk rising edge) to tx serial lines (the first bit of 10-bit symbol) 25 - 30 ns t rx-lat receive latency, time for data moving from rx serial lines (the first bit of 10- bit symbol) to mac interface (pclk rising edge) 48 - 54 ns 7.3 transition time of power state table 7.3 ? transition time of power state symbol parameter min typ max unit t p0s-p0 time for phy to return to p0, after having been in p0s. time is measured when pd[1:0] are set to p0 until the phy asserts physts 52 - 74 ns t p1-p0 time for phy to return to p0, after having been in p1. time is measured when pd[1:0] are s et to p0 until the phy asserts physts 52 - 74 ns t p2-p1 time for phy to return to p0, after having been in p2. time is measured when pd[1:0] are set to p0 until the phy asserts physts 16 - 17 s t p0-p0s time for phy to return to p0s , after having been in p0 . time is measured when pd[1:0] are set to p0 until the phy asserts physts 52 - 74 ns t p0-p1 time for phy to return to p1 , after having been 52 - 74 ns
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 36 in p0 . time is measured when pd[1:0] are set to p0 until the phy asserts physts t p0-p2 time for phy to return to p2 , after having been in p0 . time is measured when pd[1:0] are set to p0 until the phy asserts physts 16 - 17 s
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 37 7.4 power consumption power consumption with 2-lanes and 4-lanes operatio n table 7.4 ? typical power consumption with 2-lanes, 4-lanes, and 1.2v differential peak to peak output voltage current at 2.5v (ma) current at analogue 1.8v (ma) current at digital 1.8v (ma) current at reference voltage 1.25v (ma) operation condition power state operation mode power consumption (mw) 184 285 128 0 all on p0 8-bit @250mhz pclk, 4-lanes 1203.4 14 207 89 0 pll on tx idle rx on p0s 8-bit @250mhz pclk, 4-lanes 567.8 14 174 48 0 pll on tx idle rx idle p1 8-bit @250mhz pclk, 4-lanes 434.6 9 146 10 0 pll off tx idle rx idle p2 8-bit @3.13mhz pclk, 4-lanes 303.3 107 161 81 0 all on p0 16-bit @125mhz pclk, 2-lanes 703.1 17 117 65 0 pll on tx idle rx on p0s 16-bit @125mhz pclk, 2-lanes 370.1 17 101 45 0 pll on tx idle rx idle p1 16-bit @125mhz pclk, 2-lanes 305.3 9 74 9 0 pll off tx idle rx idle p2 16-bit @1.56 mhz pclk, 2-lanes 171.9
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 38 power consumption with single-lane operation table 7.5 ? typical power consumption with single-l ane and 1.2v differential peak to peak output voltage current at 2.5v (ma) current at analogue 1.8v (ma) current at digital 1.8v (ma) current at reference voltage 1.25v (ma) operation condition power state operation mode power consumption (mw) 51 90 65 0 all on p0 8-bit @250mhz pclk 406.5 10 72 56 0 pll on tx idle rx on p0s 8-bit @250mhz pclk 255.4 10 65 45 0 pll on tx idle rx idle p1 8-bit @250mhz pclk 223 6 37 7 0 pll off tx idle rx idle p2 8-bit @3.13mhz pclk 94.2 59 90 57 0 all on p0 16-bit @125mhz pclk 412.1 12 71 49 0 pll on tx idle rx on p0s 16-bit @125mhz pclk 246 12 64 38 0 pll on tx idle rx idle p1 16-bit @1.56 mhz pclk 213.6 6 36 6 0 pll off tx idle rx idle p2 16-bit @125mhz pclk 90.6
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 39 7.5 differential transmitter and receiver serial ou tput transmitter serial output table 7.6 ? transmitter serial output symbol parameter min typ max unit ui unit interval 399.88 400 400.12 ps v tx-diffp-p differential peak to peak output voltage 0.8 - 1.2 v v tx-de-ratio de- emphasized differential output voltage (ratio) -3.0 -3.5 -4.0 db t tx-eye minimum tx eye width 0.7 - - ui t tx-eye-median-to-max-jitter maximum time between the jitter median and maximum deviation from the median - - 0.15 ui t tx-rise , t tx-fall d+/d- tx output rise/fall time 0.125 - - ui v tx-cm-acp rms ac peak common mode output voltage - - 20 mv v tx-cm-dc-active-idle-delta absolute delta of dc common mode voltage during l0 and electrical idle 0 - 100 mv v tx-cm-dc-line-delta absolute delta of dc common mode voltage between d+ and d- 0 - 25 mv v tx-idle-diffp electrical idle differential peak output voltage 0 - 20 mv v tx-rcv-detect the amount of voltage change allowed during receiver detection - - 600 mv v tx-dc-cm the tx dc common mode voltage 0 - 3.6 v i tx-short tx short circuit current limit - - 90 ma t tx-idle-min minimum time spent in electrical idle 50 - - ui t tx-idle-set-to-idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered set - - 20 ui t tx-idle-to-diff-data maximum time to transition to valid tx specifications after leaving an electrical idle condition - - 20 ui rl tx-diff differential return loss 12 - - db rl tx-cm common mode return loss 6 - - db z tx-diff-dc dc differential tx impedance 80 100 120 l tx-skew lane-to-lane output skew - - 500 + 2ui ps c tx ac coupling capacitor 75 - 200 nf tcrosslink crosslink random timeout 0 - 1 ms
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 40 receiver serial output table 7.7 ? receiver serial output symbol parameter min typ max unit ui unit interval 399.88 400 400.12 ps v rx-diffp-p differential input peak to peak voltage 0.175 - 1.2 v t rx-eye minimum receiver eye width 0.4 - - ui t rx-eye-median-to-max-jitter m aximum time between the jitter median and maximum deviation from the median - - 0.3 ui v rx-cm-acp ac peak common mode input voltage - - 150 mv rl rx-diff differential return loss 15 - - db rl rx-cm common mode return loss 6 - - db z rx-diff-dc dc differential input impedance 80 100 120 z rx-dc dc input impedance 40 50 60 z rx-high-imp-dc powered down dc input impedance 200k - - v rx-idle-det-diffp-p electrical idle detect threshold 65 - 175 mv t rx-idle-det-diff-entertime u nexpected electrical idle enter detect threshold integration time - - 10 ms l rx-skew total skew - - 20 ns 7.6 recommended operating conditions table 7.8 ? temperature range symbol parameter min typ max unit t junctoin junction operating temperature range 0 - 125 t a operating ambient temperature range 0 - 75 t stg storage temperature range -40 - 150 table 7.9 ? thermal characteristics symbol parameter min typ max unit ja (0 m/s) - 33.2 - /w ja (1 m/s) - 28.7 - /w ja (2 m/s) thermal resistance from junction to ambient ps: ?(x m/s)? means the air flow velocity (jedec jesd51-6 moving air, maximum refl ow temperature for smt is 255 ~260 ) - 27.5 - /w jt thermal characterization parameter from junction-to-top center (jedec jesd51-2 still air, maximum reflow temperature for smt is 255 ~260 ) - 0.39 - /w jc thermal resistance from junction to case (jedec jesd51-2 still air, maximum reflow temperature for smt is 255 ~260 ) - 12.3 - /w
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 41 chapter 8 pipe timing characteristics 8.1 input setup, hold time and output timing figure 8.1 ? definition of input setup and hold tim e
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 42 figure 8.2 ? definition of output timing table 8.1 ? input setup, hold time and output timin g for 8-bit sdr mode symbol parameter min typ max unit t cycle pclk cycle time 3.99 4 4.01 ns duty- h duty cycle for pclk high 35 - 50 % t is input setup time requirement 1 0.8 - - ns t ih input hold time requirement 1 1 - - ns t co clock to output delay 2 - - 3.2 ns t oh output hold time 2 1 - - ns note: 1. based on data rise time=1.9ns, fall time=1.3ns, a nd the slew rate is based on 20%~80% measuring. 2. the test load is 10 pf. 3. all setup, hold and tco numbers include pclk jitt er and sso, which is about +/- 250ps.
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 43 table 8.2 ? input setup, hold time and output timin g for 8-bit ddr mode symbol parameter min typ max unit t cycle pclk cycle time 7.98 8 8.02 ns duty- h duty cycle for pclk high 48 - 50 % t is input setup time - - 1.4 ns t ih input hold time 0.5 - - ns t co clock to output delay - 1.5 1.6 ns t oh output hold time 0.8 1 - ns note: this table is based on design target, correlation d ata will be posted later. table 8.3 ? input setup, hold time and output timin g for 16-bit mode symbol parameter min typ max unit t cycle pclk cycle time 7.98 8 8.02 ns duty- h duty cycle for pclk high 48 - 50 % t is input setup time - - 1.4 ns t ih input hold time 0.5 - - ns t co clock to output delay - 5.3 5.6 ns t oh output hold time 4.3 4.7 - ns note: this table is based on design target, correlation d ata will be posted later. table 8.4 ? input setup, hold time and output timin g for 10-bit sdr mode symbol parameter min typ max unit t cycle pclk cycle time 3.99 4 4.01 ns duty- h duty cycle for pclk high 35 - 50 % t is input setup time - - 1 ns t ih input hold time 1 - - ns t co clock to output delay - 4 4.2 ns t oh output hold time 3.4 3.7 - ns note: this table is based on design target, correlation d ata will be posted later.
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 44 table 8.5 ? input setup, hold time and output timin g for 10-bit ddr mode symbol parameter min typ max unit t cycle pclk cycle time 7.98 8 8.02 ns duty- h duty cycle for pclk high 48 - 50 % t is input setup time - - 1.4 ns t ih input hold time 0.5 - - ns t co clock to output delay - 4.1 4.3 ns t oh output hold time 3.5 3.7 - ns note: this table is based on design target, correlation d ata will be posted later. 8.2 reference timing information table 8.6 ? reference timing information symbol parameter min typ max unit t recdet time for receiver detection - 10 - us t physts-reset timing from de- asserting rst_n to the falling edge of physts - 16.7 - us t reset reset assertion time to gl9714 10 - - us
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 45 chapter 9 package dimension figure 9.1 - gl9714 233 pin lfbga package
gl9714 pci express tm pipe x4 phy ?2004-2007 genesys logic inc. - all rights reserved . page 46 chapter 10 ordering information table 10.1 - ordering information part number package green version status GL9714-TGGXX 233-pin lfbga green package xx engineering sample

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